TweakTown

Cadence teases PCIe 7.0 hitting 128GT/s with optical PCIe connections, successor to CopprLink

Use left and right arrow keys to seek audio. Cadence stole the show recently at the PCI-SIG DevCon 2024 event, and in honor of the 32nd anniversary of the PCI-SIG Developer's Conference, Cadence ...
Semiconductor Engineering

Getting Ready For An Efficient Shift To PCI Express 6.0 Designs With Optimized IP

PCI Express (PCIe) 6.0 technology with key changes will bring about challenges that high-performance computing, artificial intelligence, and storage system-on-chip (SoC) designers will face. This ...
Semiconductor Engineering

High-Speed Manufacturing And In-Field Scan Test Access Via PCI Express For GPIO Limited SoCs

Today’s huge, deep submicron system on chip (SoC) designs present many challenges at every stage of development, from architectural exploration to volume production. This post addresses the specific ...
Electronic Design

Agilent Introduces Solution for PCI Express 3.0 Receiver Characterization

January 29, 2013. Agilent Technologies Inc. at DesignCon announced an enhanced solution for PCI Express 3.0 receiver characterization. The Agilent PCIe 3.0 receiver characterization solution provides ...